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PowerViews
Driving Paralleled IGBTs
Alan Ball, IGBT Applications Engineering Manger, ON Semiconductor
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To test the gate resistor configuration options, two IGBTs were chosen from a group of 22 parts. The two chosen devices were selected for their mismatch. The devices tested were NGTB40N60IHL IGBTs manufactured by ON Semiconductor. These are 600 volt, 40 amp devices. Units 1 and 26 were selected for their differences in both parameters. Their turn-on losses were 1.65mJ and 1.85mJ respectively and their turn off losses were 0.366mJ and 0.390mJ respectively.
Using a single driver and separate 22Ω gate resistors, the imbalance in the current waveforms at turn off was quite noticeable and was due to the mismatch in switching speeds along with differences in the threshold, transconductance and gate charge characteristics for the two devices. Substituting a common 11Ω gate resistor forces both gates to be at the same potential at any given time. The imbalance at turn off is greatly reduced with this configuration, and the DC imbalance is not affected by the configuration of gate resistors.
Since the possibility of oscillations between devices can not be determined until the system is designed and a prototype built, it is recommended that a gate circuit be used that can accommodate individual, common and a combination of gate resistors.
Gate Resistor Schematics (click to view larger image)
The combinational schematic offers the flexibility of adjusting the values of the gate resistors based on the parasitic impedances of the actual circuit. If some oscillation is observed with a common resistor, the resistive gate impedance can be divided into a common and an individual component. For optimum performance, the individual resistors should account for as much of the gate resistance as possible without the risk of oscillations. This circuit can easily be tuned in a functional unit under a range of operating and environmental conditions. In this manner, the gate voltages can be held as close as possible to the same potentials during turn on and turn off, but some individual resistance can be added when necessary to assure that the devices do not oscillate with each other.
Achieving optimal performance in a high-power, parallel application allows for maximum system reliability and maximum performance. The gate drive considerations discussed herein, are one of the factors that will optimize a high-power switching system.
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About the Author
Alan Ball has over 30 years experience in power supply design and analysis, encompassing both military and commercial power supply design. He has been with ON Semiconductor for the past 10 years and held various application engineering positions and holds approximately 12 patents. Prior to joining ON Semiconductor he worked for Power Paragon as an engineering manager and general manager of the Airborne Power division. He holds a BSEE from Arizona State University, and an MBA from Keller Graduate School of Management.
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