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Diwakar Vishakhadatta joins Intersil as VP of Product Development

April 08, 2014 by Jeff Shepard

Intersil Corporation today announced the appointment of Diwakar Vishakhadatta as vice president of product development. Mr. Vishakhadatta brings to the role a strong technical acumen and a successful track record of managing complex development projects and achieving a high level of R&D execution. His background will enable him to immediately contribute to the momentum the company established last year as it focused its strategy and began expanding R&D resources to support compelling road maps in power management and precision analog.

"We have a strong, innovative and growing technical team at Intersil. With rigorous new product selection discipline coupled with consistent design execution, we have the ability to gain leading share in our target markets," said Necip Sayiner, president and CEO of Intersil Corporation. "Diwakar has a unique combination of technical depth and design management experience that will be instrumental in establishing the methodologies and best practices required to achieve the high bar we've set for design execution and engineering efficiency."

Mr. Vishakhadatta joined Intersil from Silicon Labs, where he was most recently vice-president and general manager. He was responsible at various times during his tenure there for development, applications and marketing of the broadcast audio, microcontroller, wireless and power product lines. Mr. Vishakhadatta rejoined Silicon Labs from ST-Ericsson, where he was vice president responsible for all engineering development and system architecture for the single-chip phone and cellular products acquired from Silicon Labs.

Prior to ST-Ericsson, Mr. Vishakhadatta was a design director for Silicon Labs wireless products. He also held various design manager and design engineering roles at Cirrus Logic. Mr. Vishakhadatta has a B.S.E.E. from the Indian Institute of Technology and an M.S.E.E from Oregon State University He has 26 issued and 39 pending patents.